NSF Sponsored Workshop on Structured Design Methods for MEMS

Position Paper

John Tanner
Tanner Research, Inc.
180 North Vinedo Avenue
Pasadena, CA 91107

Tanner Research aims to deliver tools and libraries to the electronics designer's desktop (network)---tools that are easy to use, and are available on the most popular platforms at affordable prices. Our goal is to provide MEMS designers with a powerful, highly integrated, state-of-the-art design tool suite by leveraging off of our existing VLSI CAD tools.

Our roots are in the Mead-Conway methodology for the design of VLSI. We have developed a suite of commercial IC design tools that are currently used by a variety of MEMS designers. Our IC and Multi-Chip Module (MCM) tools of interest to MEMS designers include:

Under government funding, we are nearing completion of the following enhancements to our tools to better support MEMS:

Under government funding, we are beginning an investigation of the following features for MEMS:

In addition, we believe the following tools are needed:

We see similarities and differences between MEMS and VLSI designs. They both benefit from full hierarchical layout design and a mixture of hand-crafted cells and algorithmic code-based synthesis. MEMS needs a richer set of layout capabilities including arcs as drawing primitives, all-angle rotations, and all-angle DRC and extraction.

As others have noted, MEMS allows the design of a much richer set of devices than in the IC world where there are just a few kinds of transistors. Thus the tools for the extraction of netlists from geometry, tools that for VLSI can discover devices as well as interconnect, will be limited for MEMS designs to discovering the interconnect between predefined hierarchical cells. However, as MEMS designers move from a test/prototype environment to a production environment, tools such as our block extractor become important for back end validation.

As with VLSI, simulations of MEMS devices of significant size cannot be done at the finest detail within the limits of computing memory and simulation time available on the desktop (network). Simplifying abstractions must be made to reduce the simulation load while still maintaining the behavior of interest. In VLSI, levels of abstraction range from finite- element (TCAD) through circuit-level, gate-level, and behavioral (HDLs). For MEMS, levels of abstraction range from finite-element through circuit level (with mechanical behavior) to behavioral level.

In both disciplines, the simplifications come from abstracting away some significant level of detail. The designer is best at determining the essential desired behavior and thus higher levels of abstraction are almost always defined by the domain expert. Computationally intensive tools could be used to perform analysis and simulations, under the experimental control of the modeler, to verify that a more abstract model simulation matches close enough to the more detailed one.

We allow researchers and designers to extend our tools by writing their own C-language routines that link into our tools or are interpreted by our tools. This mechanism allows researchers to leverage our efforts to provide robust multi-platform base functionality while adding their own innovations with minimal overhead. This method of collaboration only works if we provide the right set of extension hooks into our tools.

Perhaps it is our VLSI bias, but we foresee a large and very interesting set of MEMS chips that will contain a small number of mechanical elements integrated closely with electronics. In this scenario, it is critical that the new MEMS aspects of design be incorporated into the existing, well-proven IC design tools and procedures. This view drives our development to add new MEMS capability to our integrated tool set.

At the upcoming NSF workshop, we hope to gauge the importance of the list of tools that we have identified above that are lacking, learn about other tool needs, and identify the areas that our tools need hooks for user extensions.

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