NSF Sponsored Workshop on Structured Design Methods for MEMS

Synthesis of MEMS


In recent years, computer-aided design tools for the synthesis of VLSI integrated circuits have been a topic of research and development. Synthesis strives to proceed from a high-level behavioral or structural description of a VLSI system down to low-level mask geometry. The various VLSI synthesis levels build upon the mask geometry layout editors that are the designer's interface to the fabrication process.

Arguably, "structured-custom" synthesis paradigms in digital VLSI (hybrid gate arrays, standard cells, chip assembly, parameterizable cores) and rapid prototyping methodologies (field programmable logic and interconnect devices) are "success stories". There has been greater progress in synthesis tools for digital VLSI systems than for analog VLSI systems. The analogy of microelectromechanical systems (MEMS) to analog VLSI may be more appropriate than an analogy to digital VLSI. Many position papers at the May 1994 NSF New Paradigms for Manufacturing workshop NSF:94 noted the limits of the analogy between VLSI systems and mechanical systems, particularly with respect to the design process, and implicitly with respect to the prospects for developing "synthesis" tools for mechanical systems.

Our own general session and breakout discussions, while specific to microelectromechanical systems, have recapitulated the general findings of previous workshop attendees:

  1. VLSI has a "complete basis" (the NOR gate), while MEMS does not;
  2. VLSI has a "clean separation" between function/design and fabrication/process, while MEMS does not;
  3. VLSI has mathematical constructs (Boolean algebra, correct-by-construction synthesis, etc.), while MEMS does not, and
  4. VLSI operates on (digital) information and has no moving parts, while MEMS operates in multiple coupled energy domains and has mechanical structures.
Recent research in MEMS has focused on inertial sensors, micro-optics, micro-robots for assembly, and micro-manipulation. The richness of possible applications, and the complexity of contemplated systems (e.g., micro-robots), suggest a great deal of potential for synthesis technology for MEMS. Analogous to the situation in VLSI, synthesis tools for MEMS must operate on several views of the design:
  1. from desired 3-D geometry (device cross-sections) to process and mask specifications;
  2. from electro-mechanical circuit to component geometry specification; and
  3. from high-level, functional description of the hardware to electro-mechanical circuit specification.

Overview of VLSI Synthesis

Synthesis, in the VLSI context, connotes "something other than custom or hand-crafted". Today, elements of the VLSI synthesis process contain a number of different design levels and a collection of CAD tools to convert from level to level. At the highest level are Hardware Description Languages (HDL). These languages can include a behavioral and/or functional description of the system. The various hierarchical levels of abstraction correlate well with stages in a standard "design flow".

From the HDL, a synthesis system would contain a CAD tool with algorithms which can apply transformations to produce an intermediate design representation. This intermediate design representation may be at the control-data flow graph or Boolean network levels. Another CAD tool may then input the control-data flow graph and search for area and time design trade-offs within the space of feasible (i.e., correct) designs. This design trade-off analysis tool would output a revised list of hardware resources and a control "schedule" in a structure description language format.

At the next lower level, algorithms which map the revised intermediate design representation to a library of component "macros" (RTL-level blocks, standard-cell, etc.), would be invoked. This process is essentially performed via a covering formulation. At the lowest level, there will be algorithms which embed the physical design and its connection topology onto silicon resources. A number of reasonably well-established CAD tools will handle the placement and routing tasks and produce a final CIF or GDS II mask geometry file if the design is to be produced via a typical CMOS process.

Issues for MEMS Synthesis

From the above discussion of a typical VLSI synthesis system, a number of similarities and differences exist when trying to propose a synthesis systems for MEMS. These include:

Findings and Recommendations

Synthesis is complementary to analysis which includes the tasks of extraction and simulation. Accompanying each step from a given level to the next higher level is an extraction, whereby the output of analysis at one level can be used for analysis at the next higher level. It is important to have sufficient analysis tools so that goals such as the following can be met successfully:

  1. top-down design from a functional or other high-level specification, or
  2. iterative design that includes semi-automatic exploration of the design space and achieves short design cycles.
The following summary lists suggested directions and motivations for several broad levels at which synthesis for MEMS should be developed. To organize the findings and recommendations, Table 1 shows the different "levels" of MEMS design. The synthesis process involves traversing this figure from the top system level down to the bottom process-mask level. Conversely, analysis involves traversing this figure from the bottom up. Each of the subsections below relates to the tasks needed to proceed from one level of the table to the next level below.
Table 1: Goals for Synthesis Research from System Issues down to Process and Mask. Synthesis Proceeds Downward while Analysis Proceeds Upward.
Synthesis Level3 Year goal10-Year goal
SYSTEM Lang. requirements HDL language
Model including (dynamics) HDL to schematic synthesis Formal design and verification methods
Diagnostic structures Resource allocation
Packaging, assembly and identification
MULTI-DOMAIN SCHEMATIC 2D mech-electrical Chemical, magnetic fluidic and thermal
Library: actuator, spring, mass, damper elements Other domains
Place & route cues
Shape synthesis
COMPONENT Tool prototype 3D shape generator
Physical shape (structure) 2D shape generator (homogenization) Yield/cost analysis tools
Layout generator with component library for fixed processes Process variation compensation tools
Process compiler (MISTIC) Implement & distribute process compiler such as Tanner, CaMEL
PROCESS | MASK Extensions to bulk micromachining mask/layout Assembly sequence synthesis
Develop process library technology file Reliability
DRC & extraction for specific processes


Despite the differences between digital VLSI and MEMS, sufficient parallels exist to recommend a program of research to develop (semi-)automated methods for synthesizing at least some classes of MEMS devices. The differences between digital VLSI and MEMS strongly suggest that structured MEMS synthesis methods will not be a direct outgrowth of VLSI methods, however, many of the underlying constructs (e.g., language, modeling, simulation, etc.) should be similar in philosophy, and appear likely to serve as guides for initial research in this area.

VHDL-A appears to be an appropriate starting place for synthesis language-related research. The development of libraries of previously successful designs is also important, but can proceed (at best) in parallel with synthesis language development. Approaches to transforming a description (perhaps of the function) of a desired device into a description of the physical device (including translation-like methods as well as search methods) have a great deal of promise for synthesis of MEMS devices, and research in this area should be encouraged.

Previous: Workshop Discussion Group Reports
Next: Simulation of Function Group Report
Return to NSF MEMS Design Workshop Index