NSF Sponsored Workshop on Structured Design Methods for MEMS

A Language for MEMS

Amar Mukherjee
Dept. of Computer Science
University of Central Florida
Orlando, FL 32816

This Workshop is the third in the series of Workshops sponsored by NSF on design methodologies for VLSI-like technologies. First, I would like to present a brief summary of ideas on design hierarchy that were discussed at the prior Workshops. I will then outline a set of requirements for a possible layered language to describe MEMS structures.

Structured Design Methodology

Development of a structured design methodology played a key role in the VLSI (Very Large Scale Integration) revolution. In this methodology, the operation of the circuit is abstracted at different levels by formal systems, which allows separation between system design, component design and fabrication. The key element that contributed to this clean digital interface was the discovery of a set of scalable design rules (Mead and Conway,1980) allowing processing steps to be defined independent of object's geometry. For mechanical and electromechanical systems, in general, multilevel design hierarchy does not work very well because the underlying models involve energy transformation and physical parameters; the elemental components share function and behave differently in a system due to back loading (Voelcker, 1994 and Whitney, 1994). Even for VLSI, the traditional design hierarchy (system, function, logic, circuit, layout and fabrication) breaks down if we bring in performance considerations like power, timing, speed and chip area (Mukherjee, 1986). The design may need multiple iterations to take into account the side-effects of specially designed leaf cells which influence all the layers above. In fact, the exact behavior of the device can only be described by an analog model. For mechanical design, the performance considerations are an integral part of the design process. The shape and geometry of the part can be described by a geometry modeler but its functional behavior cannot be guaranteed unless the material satisfies certain physical properties and its geometrical dimensions satisfy certain size constraints depending on the application and performance requirements. The limits on geometric dimensions of the object and physical attributes of the material as they relate to correct function and performance of the object will be called design constraints. The design constraints are process independent and can be derived by experimental methods and mathematical modeling. This terminology is adopted in order to distinguish between factors affecting functionality and the manufacturability of the part. In the context of VLSI design, these two considerations can be merged into a set of conservative geometric design rules. An analogous set of design rules must also be satisfied by the mechanical fabrication process.

The design hierarchy consists of levels of abstractions, data exchange languages and digital interfaces as shown in Figure 1. The design subsystem performs the traditional design by deriving the shape and geometry that achieves the desired function and specification. The design must satisfy a set of design constraints with respect to a set of relevant mechanical and physical properties of the material. The analysis and simulation tools verify the correctness of the design. The design may go through multiple refinements before being delivered via the three-dimensional digital interface (Sproull,1994) to the physical design layer.

                        |   DESIGN    |
                        o-------------o     Functional
                               |            Design
                        |  FUNCTIONAL |
                        |  SIMULATION |
     3-D INTERFACE             |
     SIF (Solid Interchange    |
          Format)       o-------------o
                        |    SLICER   |
                        o-------------o     Physical
                               |            Design
                        | DESIGN RULES|
                        | VERIFICATION|
      2.5-D INTERFACE          |
      L-SIF (Layered Solid     |
      Interchange Format o------------o
                         | PROCESS    |
                         | PLANNING   |
                         o------------o     Fabrication
                         |FABRICATION |
Figure 1: Design Hierarchy

The design languages to be used for data exchange at the digital interfaces are areas of active research. A proposal for a new language, called SIF (Solid Interchange Format) has been advocated by Sequin at the last NSF Workshop (Sequin and McMains, 1995). Such a language should probably be based on a solid modeling system such as CSG (Constructive Solid Geometry) or BREP (Boundary Representation), possibly augmented by non-uniform rational B-spline (NURBS) surfaces and should form the basis of a standard 3-D data exchange language.

The physical design phase uses specific knowledge of the process and its design rules to specify a 2.5-D description of the part. Ideally, like in VLSI which satisfies layering paradigm with conservative design rules, this stage should be insensitive to the object's geometry. As is well known from studies of SFF processes, such a layering paradigm does not work in practice for objects with undercuts, objects with multigraded material or with material having anisotropic density. Furthermore, the smooth three dimensional surface features have to be compromised by linear approximation of zigzag surface features and additional constraints are put if the object needs support structures or overhangs.

The translation of the 3-D geometry to 2.5-D geometry has to be done by a 'slicer' that will produce the 2.5-D layers, given its description in SIF. A language called L-SIF (layered solid interchange format) has been suggested for this layered description but no specifics have been provided for any SFF process (Sequin and McMains, 1995 and Finger et al., 1995). This description will form a 2.5-D digital interface between the physical design and the process planning stage.

One key software is a design rules checker. The purpose of the design rules checker is to ensure the feasibility of the part fabrication. The tolerances of the fabricator must be reflected in the translator output of the slicer.

For VLSI design, the 3-D and the 2.5-D digital interfaces merged into one interface, the design rules allowed a clean separation between design and fabrication hiding the process planning steps in the set of masks required for a standard process. For MEMS, the processing steps depend on object's geometry.

The Language L-SIF (Layered Solid Interchange Format)

Surface micromachining uses a lyering paradigm that comes close to the VLSI layering and evolved with a strong motivation to use the VLSI fabrication facility in "as is" condition. In fact, it is simpler than VLSI since the process does not have to produce "active" components like transistors nor does it have to take into account the electrical parameters (the so-called "parasitics") that influence the connectivity considerations and the performance of the chip. Essentially there are three kinds of material that need to be layered to produce the desired parts: the structural layer, the sacrificial layer and the insulation layer. A different set of considerations such as deformation due to residual compressive stress, frictional properties and coupling phenomena such as stiction or bearing clearances come into the picture. If the domain of geometry is restricted to simple structures with a set of special standard constructs like bushing, bearing, cantilever, gear, rotor etc., a simple geometry language like CIF will serve the purpose. For bulk micromachining, several complicating factors arise which do not connect the layered description of the structures with the underlying process steps. The geometry for bulk micromachining seems to be the result of a sequence of anisotropic etching and etch stops that are custom made for the device. A geometric representation of a diaphragm, a hole, a cavity, a pin or a cantilever can still be defined with an implied semantics of how anisotropy is used to produce such a structure. Such special constructs have also been used for VLSI; 'butting' or 'buried' contacts or 'via' or even the I/O pads are examples of such special constructs.

To incorporate arbitrary 3-D geometry, a more powerful layered language, L-SIF, will be necessary. Current implementation of surface micromachining such as MUMPS use CIF/GDS format or some variants or IGES format which can only handle polyhedral representations of solid. Special cell libraries of frequently used parts with non-polyhedral surfaces have also been provided in some instances. There is a need to develop a standard layered language, called L-SIF, for MEMS.

L-SIF will include the basic geometric constructs of CIF (Mead and Conway, 1980) which are:

Polygon with a path.
Box with length, width,center and direction.
Round flash with diameter and center.
Wire with width and path.

The layer attribute of CIF (which identifies polysilicon, metal, diffusion etc.) will be the same in L-SIF identifying the material of the layer in question. Since L-SIF will handle more complex geometry than CIF (which only handles Manhattan blocks and cylinders), L-SIF will have primitives that capture any slice of a quadric body such as sphere, ellipsoid, cone, paraboloid and hyperboloid with arbitrary orientation of the plane that cuts the slice. Extension of the language to cover bodies expressed by NURBS is also possible. The language will include constructs like:

[ Layer name, quadric object, vertical resolution, orientation vector, slice number ]

The object will be defined by its mathematical parameters. For example, for an ellipsoid we specify the coordinate of the center and the distances of its three radii. The orientation vector specifies the three components of a vector that defines the object's rotation around the three major axes x,y and z. After placing the object on a horizontal plane with this orientation, imagine slices being cut in the vertical direction with the resolution factor provided and the slice number identifies which cut is the present cut being used.

The language should be able to describe layers with internal hollow regions. The "concentric" holes is defied as

[Concentric: label, scale factor]
where "label" inside the square bracket identifies a slice as before and scale factor defines a scaled down version of the object. The object consists of the labeled object from which the scaled down portion has been removed. The Boolean operations on layers like union, intersection or difference are defined as usual.

The L-SIF language will also have some of the general features that are allowable in CIF such as symbol definition, call, delete and user extension, comment etc. and the usual syntax of data types.

CIF is a standard data exchange language that can be mapped to different target technologies. Similarly, L-SIF should become a standard data exchange language for all SFF processes including MEMS which can be mapped to specific target technologies like surface, bulk or LIGA processes with its associated set of "libraries" of special constructs.


  1. Mead, C. and Conway, L., 1980, "Introduction to VLSI Systems", Addison-Wesley.
  2. Mukherjee, A., 1986, "Introduction to nMOS and CMOS VLSI Systems", Prentice Hall.
  3. Mukherjee, A. and Hilibrand, J., eds., 1994, "New Paradigms for Manufacturing", MIPS Division, CISE, National Science Foundation, Arlington, Virginia, May 2-4, 1994.
  4. Sequin, Carlo H. and McMains, Sara, "What Can We Learn from the VLSI CAD Revolution?", paper presented at the NSF Workshop on Design Methodologies for Solid Freeform Fabrication, Carnegie Mellon University, June 3-5, 1995.
  5. Sproull, R. F., "Digital Interfaces to Fabrication", Proc. Workshop on New Paradigms for Manufacturing, NSF, Arlington, VA, May 2-4, 1994.
  6. Voelcker, H., 1994, "New Paradigms for Mechanical Design & Manufacturing", Proc. Workshop on New Paradigms for Manufacturing, NSF, Arlington, VA, May 2-4, 1994.
  7. Whitney, D. E., 1994, "Some Differences Between VLSI Fabrication", Proc. Workshop on New Paradigms for Manufacturing, NSF, Arlington, VA, May 2-4, 1994.

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